1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to a method for forming vertical interconnects between adjacent metal layers which are separated by polyimide insulating layers.
Semiconductor fabrication requires the formation and patterning of conductive metallization layers, typically aluminum or aluminum silicon, to define interconnections between various circuit elements formed in the device substrate. For products having a high density of such circuit elements, such as very large scale integration (VLSI) products, it is normally necessary to form two or more metallization layers which are vertically spaced apart and separated by intermediate insulating layers. The insulating layers are usually formed from silicon dioxide, although the use of polyimide insulating layers offers a number of advantages and is finding increasing use. The present invention concerns the formation of multiple metallization layers having intermediate polyimide insulating layers.
One problem encountered in the formation of multiple metallization layers results from the propagation of surface irregularities. The patterning of each metallization layer results in an uneven surface whose contours are imparted to the overlying insulating layer. The primary advantage of polyimide insulating layers over silicon dioxide insulating layers is that the polyimide layers smooth over the irregularities of the underlying metallization layers, providing a superior surface for applying additional metallization layers, and the like. The polyimide insulating layers are also free from discontinuities, such as small holes, which are frequently found in silicon dioxide insulating layers.
The polyimide insulating layers, however, suffer from certain drawbacks related to the formation of holes for the vertical interconnects or vias which are required to electrically connect the vertically spaced apart metallization layers. Because of the generally slower or compatible etch rate of polyimides relative to the photoresist materials, it has been difficult to form the vertical interconnect holes by conventional photolithographic techniques. To overcome this problem, it has been necessary to form an intermediate hard layer, typically silicon dioxide or aluminum, between the polyimide layer and the photoresist layer. The photoresist is then used to pattern the hard layer by conventional techniques, and the patterned hard layer is then used as the mask for forming the vertical interconnects. The intermediate hard layer then must be removed prior to applying the next metallization layer. Although workable, this method is cumbersome and it would be desirable to provide a method for etching the vertical interconnect holes directly without requiring the formation of an intermediate masking layer.
In addition to being cumbersome, the method just described has an additional drawback. The use of an oxygen plasma to etch the polyimide layer through the hard layer mask causes the formation of concave walls of the vertical holes in the polyimide layer. Such concave walls can create breaks in the step coverage in the overlying metallization layers. It would therefore be desirable to provide a method for forming the vertical holes which results in straight walls or walls which diverge in the upward direction.
2. Description of the Background Art
Adams and Capio (1981) J. Electrochem. Soc. 128:423-429 describe a method for planarizing a phosphorous-doped silicon dioxide insulating layer by applying a layer of photoresist over the silicon dioxide to define a smooth surface and then sputter etching the combined layers under conditions which etch the photoresist in the silicon dioxide at the same rate. U.S. Pat. No. 4,377,438 to Moriya et al. describe the planarization of a silicon nitride insulating layer using a fluorocarbon and hydrogen plasma etch.